Production of 128-layer TLC NAND begins as Flash densities increase
South Korean manufacturer SK Hynix is touting mass production of the "world's first" 128-layer 4D TLC NAND Flash chips, following the introduction of their 96-layer 4D TLC (three-bit) NAND eight months ago.
The concept of "4D" NAND is a marketing term, though it's unclear what the fourth dimension is supposed to be.
SK Hynix touts the "the industry's highest vertical stacking with more than 360 billion NAND cells, each of which stores 3 bits, per one chip," in a press release, adding that this was achieved using by applying "ultra-homogeneous vertical etching technology," "high-reliability multi-layer thin-film cell formation technology," and a lower-power design.
The number of manufacturing processes was reduced by 5% between the 96-layer and 128-layer design, the company claims a 40% bit productivity per wafer increase in the transition.
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Shipments to buyer will begin in the second half of 2019, with SY Hynix planning to release a UFS 3.1-packaged version of this technology for smartphone and tablet users in 2020, as well as planning a 2TB consumer SSD, as well as 16TB and 32TB NVMe SSDs for data centers.
Flash NAND manufacturers have been selling products with 128-layer QLC (four-bit) NAND for some time, though the market for QLC NAND sits roughly around 15%, due to dramatically reduced write cycles-3D TLC NAND is rated for 1,000 to 3,000 cycles, and 3D QLC NAND (four-bit) rated for 100 to 1,000 cycles. Practically speaking, there is no limit to the number of times a block can be read, making the lower-endurance QLC NAND more practicable for cases similar to WORM (write once, read many) drives, but with the performance profile of NAND Flash.
The company also announced development of 176-layer NAND Flash, though provided no details on release.
For more, check out TechRepublic's cheat sheet for Flash storage , and all the flash-y new storage technologies showcased at Computex 2019 .